TSV (Through Silicon Via) heater

Wed, 24 Jun 2026 01:07:03 +0800

On the 300mm line, TSV stacking falls apart when the thermal profile drifts. A single degree across the wafer is enough to crack vias, trash the photoresist, and wipe out a month of work. The heater has to deliver repeatable heat—not just heat. What matters under the hood We built the TSV heater around short-wave infrared elements and a quartz-ceramic assembly to keep particle generation at zero. Wafer-level uniformity holds ±0.1°C across the full diameter, and setpoint repeatability is ±0.2°C shot-to-shot. The system fits Class 1–100 cleanrooms, runs 24/7, and is rated for 5,000+ hours with under 5% output drift. Temperature ramps clear 10°C/s, so you cut cycle time without blowing the thermal budget. Why this lands in TSV processing TSV flow is lithography, etch, liner, seed, and electroplating, with photoresist bakes threaded through. You need a bake that lands in the same window every time: soft bake to pull out solvent, hard bake to lock down the mask, and a clean cool-down to protect the via stack. Our heater holds the wafer on the exact bake curve, batch after batch. The payoff is tighter critical dimension control, fewer defects, and yield you can plan around. Energy use drops, too—reach setpoint fast, hold it without overshoot. What you need to line up The platform needs a dedicated power bus and a clean gas supply. Dropping it into an older cluster tool usually means a mechanical kit and a firmware match. Plan the thermal budget across the whole stack—heater, chuck, and shield—because coupling shifts with geometry. Run a short commissioning pass to lock the recipe in, and the process stays stable from there.

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TSV (Through Silicon Via) heater